이곳은 개발을 위한 베타 사이트 입니다.
기여내역은 언제든 초기화될 수 있으며, 예기치 못한 오류가 발생할 수 있습니다.

RISC-V/명령어 목록

덤프버전 :

분류


파일:상위 문서 아이콘.svg   상위 문서: RISC-V

명령어 집합
CISCAMD64●x86● · M68K · 68xx · Z80 · 8080 · MOS 65xx · VAX
RISCAArch64 ARM · RISC-V● · MIPS● · DEC Alpha · POWER PowerPC · CELL-BE
LoongArch · OpenRISC · PA-RISC · SPARC · Blackfin · SuperH · AVR32 AVR
VLIW
EPIC		E2K · IA-64 · Crusoe


1. 개요
1.1. 약어 설명
1.2. 표기법
1.3. 명령어 인코딩
1.3.1. 명령어 길이 인코딩
1.3.2. 기본 명령어 형식
1.3.2.1. Opcode Map
1.3.3. "A" 확장
1.3.4. 압축된 명령어 형식 ("C" 확장)
1.3.4.1. Opcode Map
1.3.4.2. 3-bit Register field
1.3.5. "F", "D", "Q" 확장
1.3.6. "V" 확장
1.4. 레지스터
1.4.1. 범용 레지스터
1.4.1.1. 정수 레지스터
1.4.1.2. 부동소수점 레지스터
1.4.1.3. 벡터 레지스터
1.4.2. CSR
2. 명령어 목록
2.1. RV32I
2.1.1. ALU 레지스터-상수 연산 명령어
2.1.2. Shift immediate 명령어
2.1.3. 레지스터-레지스터 연산 명령어
2.1.4. 제어 및 조건부 분기 명령어
2.1.5. Load/Store 명령어
2.1.6. 시스템 및 I/O 명령어
2.1.6.1. FENCE
2.2. RV64I
2.2.1. 변경된 명령어
2.2.1.1. Shift immediate 명령어
2.2.2. 추가된 명령어
2.2.2.1. Load/Store 명령어
2.2.2.2. 32-bit ALU 레지스터-상수 연산 명령어
2.2.2.3. 32-bit shift immediate 명령어
2.2.2.4. 32-bit 레지스터-레지스터 연산 명령어
2.3. "Zifencei" 확장
2.4. "Zicsr" 확장
2.5. "M" 확장
2.5.1. RV32M
2.5.2. RV64M
2.5.3. Zmmul 확장
2.6. "A" 확장
2.6.1. RV32A
2.6.2. RV64A
2.7. "F" 확장
2.7.1. RV32F Load/Store 명령어
2.7.2. RV32F 연산 명령어
2.7.3. RV32F 변환 명령어
2.7.4. RV32F 이동 명령어
2.7.5. RV32F 비교 명령어
2.7.6. RV64F 변환 명령어
2.8. "D" 확장
2.8.1. RV32D Load/Store 명령어
2.8.2. RV32D 연산 명령어
2.8.3. RV32D 변환 명령어
2.8.4. RV32D 이동 명령어
2.8.5. RV32D 비교 명령어
2.8.6. RV64D 변환 명령어
2.8.7. RV64D 이동 명령어
2.9. "Q" 확장
2.9.1. RV32Q Load/Store 명령어
2.9.2. RV32Q 연산 명령어
2.9.3. RV32Q 변환 명령어
2.9.4. RV32Q 이동 명령어
2.9.5. RV32Q 비교 명령어
2.9.6. RV64Q 변환 명령어
2.10. "Zfh", "Zfhmin" 확장
2.10.1. RV32Zfh Load/Store 명령어
2.10.2. RV32Zfh 연산 명령어
2.10.3. RV32Zfh 변환 명령어
2.10.4. RV32Zfh 이동 명령어
2.10.5. RV32Zfh 비교 명령어
2.10.6. RV64Zfh 변환 명령어
2.11. RISC-V Privileged ISA
2.11.1. Trap-Return 명령어
2.11.2. 인터럽트 관리 명령어
2.11.3. 슈퍼바이저 메모리 관리 명령어
2.11.4. 하이퍼바이저 메모리 관리 명령어
2.11.5. 하이퍼바이저 가상머신 Load/Store 명령어
2.11.5.1. RV64
2.12. "C" 확장
2.12.1. 스택 포인터 기반 Load/Store 명령어
2.12.2. 레지스터 기반 Load/Store 명령어
2.12.3. 제어 및 조건부 분기 명령어
2.12.4. 상수 생성 명령어
2.12.5. 레지스터-상수 명령어
2.12.6. 레지스터-레지스터 명령어
2.12.7. Breakpoint 명령어
2.12.8. Illegal 명령어
2.13. "Zam" 확장
2.14. "Zihintl" 확장
2.15. "Zihintpause" 확장
2.16. "Zfinx" / "Zdinx" / "Zhinx " / "Zhinxmin" 확장
2.17. "Zfa" 확장
2.17.1. 상수 생성 명령어
2.17.2. 최대/최소 명령어
2.17.3. 정수 반올림 명령어
2.17.4. 모듈러 정수 변환 명령어
2.17.5. 이동 명령어
2.17.6. 비교 명령어
2.18. "B" 확장
2.19. "P" 확장
2.20. "V" 확장
2.20.1. 벡터 Load/Store 명령어
2.20.1.1. Unit-Stride Load/Store 명령어
2.20.1.2. Strided Load/Store 명령어
2.20.1.3. Vector Indexed Load/Store 명령어
2.20.1.4. Unit-Stride Segment Load/Store 명령어
2.20.1.5. Strided Segment Load/Store 명령어
2.20.1.6. Vector Indexed Segment Load/Store 명령어
2.20.1.7. 레지스터 단위 Load/Store 명령어
2.20.2. 벡터 정수 연산 명령어
2.20.3. 벡터 고정소수점 연산 명령어
2.20.4. 벡터 부동소수점 연산 명령어
2.20.5. 벡터 Reduction 연산 명령어
2.20.6. 벡터 마스크 연산 명령어
2.20.7. 벡터 Permutation 연산 명령어
2.21. "L" 확장
2.22. "T" 확장
2.23. "N" 확장
2.24. "H" 확장
2.25. "S" 확장
2.26. "J" 확장



1. 개요[편집]

RISC-V 아키텍처의 명령어 목록.


1.1. 약어 설명[편집]

  • rd : destination register. 값을 기록할 레지스터
  • rs : source register. 값을 읽고자 하는 레지스터
  • imm : 상수


1.2. 표기법[편집]



1.3. 명령어 인코딩[편집]


1.3.1. 명령어 길이 인코딩[편집]

명령어 길이basebase+2base+4
16-bit[1]xxxxxxxxxxxxxxaa
32-bit[2]xxxxxxxxxxxbbb11xxxxxxxxxxxxxxxx
48-bitxxxxxxxxxx011111xxxxxxxxxxxxxxxx...
64-bitxxxxxxxxx0111111xxxxxxxxxxxxxxxx...
(80+16*nnn)-bit[3]xnnnxxxxx1111111xxxxxxxxxxxxxxxx...
192-bit 이상x111xxxxx1111111xxxxxxxxxxxxxxxx...
[1] aa != 11[2] bbb != 111[3] nnn != 111


1.3.2. 기본 명령어 형식[편집]

종류3130:2524:212019:1514:1211:876:0
R-typefunct7rs2rs1funct3rdopcode
I-typeimm[11:0]rs1funct3rdopcode
S-typeimm[11:5]rs2rs1funct3imm[4:0]opcode
B-typeimm[12]imm[10:5]rs2rs1funct3imm[4:1]imm[11]opcode
U-typeimm[31:12]rdopcode
J-typeimm[20]imm[10:1]imm[11]imm[19:12]rdopcode
[각주]

1.3.2.1. Opcode Map[편집]
000001010011100101110111[4:2] / [6:5]
LOAD(LOAD-FP)custom-1MISC-MEMOP-IMMAUIPCOP-IMM-3248b00
STORE(STORE-FP)custom-2AMOOPLUIOP-3264b01
(MADD)(MSUB)(NMSUB)(NMADD)(OP-FP)(OP-V)custom-2/rv12848b10
BRANCHJALRreservedJALSYSTEMreservedcustom-3/rv128
=80b
11
[각주]

1.3.3. "A" 확장[편집]

종류31:27262524:2019:1514:1211:76:0
R-typefunct5aqrlrs2rs1rmrdopcode
[각주]

1.3.4. 압축된 명령어 형식 ("C" 확장)[편집]

종류의미15:131211:109:76:54:21:0
CRRegisterfunct4rd/rs1rs2op
CIImmediatefunct3immrd/rs1immop
CSSStack-relative Storefunct3immrs2op
CIWWide Immediatefunct3immrd'op
CLLoadfunct3immrs1'immrd'op
CSStorefunct3immrs1'immrs2'op
CAArithmeticfunct6rd'/rs1'funct2rs2'op
CBBranchfunct3offsetrs1'offsetop
CJJumpfunct3jump targetop
[각주]

1.3.4.1. Opcode Map[편집]
RV32C opcode map은 다음과 같다:
000001010011100101110111RV32
[15:13] / [1:0]
ADDI4SPNFLDLWFLWReservedFSDSWFSW00
ADDIJALLILUI
ADDI16SP		MISC-ALUJBEQZBNEZ01
SLLIFLDSPLWSPFLWSPJALR/JR
ADD/MV
EBREAK		FSDSPSWSPFSWSP10
16b
11

RV64C opcode map은 다음과 같다:
000001010011100101110111RV64
[15:13] / [1:0]
ADDI4SPNFLDLWLDReservedFSDSWSD00
ADDIADDIWLILUI
ADDI16SP		MISC-ALUJBEQZBNEZ01
SLLIFLDSPLWSPLDSPJALR/JR
ADD/MV
EBREAK		FSDSPSWSPSDSP10
16b
11
[각주]

1.3.4.2. 3-bit Register field[편집]
CIW, CL, CS, CA, CB 형식의 경우 3-bit 필드를 사용해 아래와 같이 레지스터를 명시한다:
RVC 레지스터 번호000001010011100101110111
정수 레지스터x8x9x10x11x12x13x14x15
ABI 이름s0s1a0a1a2a3a4a5
부동소수점 레지스터f8x9f10f11f12f13f14f15
ABI 이름fs0fs1fa0fa1fa2fa3fa4fa5
[각주]

1.3.5. "F", "D", "Q" 확장[편집]

종류31:2726:2524:2019:1514:1211:76:0
I-typeimm[11:0]rs1widthrdopcode
S-typeimm[11:5]rs2rs1widthimm[4:0]opcode
R-typefunct5fmtrs2rs1rmrdopcode
R4-typers3fmtrs2rs1rmrdopcode
[각주]

1.3.6. "V" 확장[편집]

종류3130292827:262524:2019:1514:1211:76:0
VL*nfmewmopvmlumoprs1widthvd0000111
VLS*nfmewmopvmrs2rs1widthvd0000111
VLX*nfmewmopvmvs2rs1widthvd0000111
VS*nfmewmopvmsumoprs1widthvs30100111
VSS*nfmewmopvmrs2rs1widthvs30100111
VSX*nfmewmopvmvs2rs1widthvs30100111
OPIVVfunct6vmvs2rs1vd1010111
OPFVVfunct6vmvs2rs1001vd/rd1010111
OPMVVfunct6vmvs2rs1010vd/rd1010111
OPIVIfunct6vmvs2imm[4:0]011vd1010111
OPIVXfunct6vmvs2rs1100vd1010111
OPFVFfunct6vmvs2rs1101vd1010111
OPMVXfunct6vmvs2rs1110vd/rd1010111
vsetvli0zimm[10:0]rs1111rd1010111
vsetivli11zimm[9:0]uimm[4:0]111rd1010111
vsetvl1000000rs2rs1111rd1010111
벡터 Load/Store 명령어는 각각 (LOAD-FP), (STORE-FP) opcode를 사용하며 width로 구분한다. 나머지 명령어는 OP-V opcode를 사용한다.
[각주]

1.4. 레지스터[편집]


1.4.1. 범용 레지스터[편집]


1.4.1.1. 정수 레지스터[편집]
RISC-V 기본 ISA에서는 XLEN 비트 레지스터 32개 및 pc(program counter)를 정의한다. (RV32의 경우 XLEN=32, RV64의 경우 XLEN=64)
레지스터x0x1x2x3x4x5x6x7
ABI 이름zeroraspgptpt0t1t2
레지스터x8x9x10x11x12x13x14x15
ABI 이름s0/fps1a0a1a2a3a4a5
레지스터x16x17x18x19x20x21x22x23
ABI 이름a6a7s2s3s4s5s6s7
레지스터x24x25x26x27x28x29x30x31
ABI 이름s8s9s10s11t3t4t5t6
  • zero 레지스터는 hard-wired zero 레지스터로 이 레지스터에 대한 쓰기는 무시한다.
  • pc: program counter. 현재 instruction의 주소를 저장한다.

  • 호출 규약:
    • ra, t0-6, a0-7 레지스터는 caller-saved 레지스터이다.
    • sp, s0-s11 레지스터는 callee-saved 레지스터이다.
[각주]

1.4.1.2. 부동소수점 레지스터[편집]
RISC-V 부동소수점 확장("F", "D", "Q" 등)에서는 FLEN 비트 레지스터 32개를 정의한다. (f0-f31)
레지스터f0f1f2f3f4f5f6f7
ABI 이름ft0ft1ft2ft3ft4ft5ft6ft7
레지스터f8f9f10f11f12f13f14f15
ABI 이름fs0fs1fa0fa1fa2fa3fa4fa5
레지스터f16f17f18f19f20f21f22f23
ABI 이름fa6fa7fs2fs3fs4fs5fs6fs7
레지스터f24f25f26f27f28f29f30f31
ABI 이름fs8fs9fs10fs11ft8ft9ft10ft11
  • "F" 확장: FLEN=32
  • "D" 확장: FLEN=64
[각주]

1.4.1.3. 벡터 레지스터[편집]
RISC-V 벡터 확장("V")에서는 VLEN 비트 레지스터 32개를 정의한다. (v0-v31)
[각주]

1.4.2. CSR[편집]

  • CSR 할당
CSR 주소 할당 표 [ 펼치기 · 접기 ]
CSR AddressHexUse And Accessibility
[11:10][9:8][7:4]
Unprevileged and User-Level CSRs
0000XXXX0x000-0x0FFStandard read/write
0100XXXX0x400-0x4FFStandard read/write
1000XXXX0x800-0x8FFCustom read/write
11000XXX0xC00-0xC7FStandard read-only
110010XX0xC80-0xCBFStandard read-only
110011XX0xCC0-0xCFFCustom read-only
Supervisor-Level CSRs
0001XXXX0x100-0x1FFStandard read/write
01010XXX0x500-0x57FStandard read/write
010110XX0x580-0x5BFStandard read/write
010111XX0x5C0-0x5FFCustom read/write
10010XXX0x900-0x97FStandard read/write
100110XX0x980-0x9BFStandard read/write
100111XX0x9C0-0x9FFCustom read/write
11010XXX0xD00-0xD7FStandard read-only
110110XX0xD80-0xDBFStandard read-only
110111XX0xDC0-0xDFFCustom read-only
Hypervisor and VS CSRs
0010XXXX0x200-0x2FFStandard read/write
01100XXX0x600-0x67FStandard read/write
011010XX0x680-0x6BFStandard read/write
011011XX0x6C0-0x6FFCustom read/write
10100XXX0xA00-0xA7FStandard read/write
101010XX0xA80-0xABFStandard read/write
101011XX0xAC0-0xAFFCustom read/write
11100XXX0xE00-0xE7FStandard read-only
111010XX0xE80-0xEBFStandard read-only
111011XX0xEC0-0xEFFCustom read-only
Machine-Level CSRs
0011XXXX0x300-0x3FFStandard read/write
01110XXX0x700-0x77FStandard read/write
0111100X0x780-0x79FStandard read/write
011110100x7A0-0x7AFStandard read/write debug CSRs
011110110x7B0-0x7BFDebug-mode-only CSRs
011111XX0x7C0-0x7FFCustom read/write
10110XXX0xB00-0xB7FStandard read/write
101110XX0xB80-0xBBFStandard read/write
101111XX0xBC0-0xBFFCustom read/write
11110XXX0xF00-0xF7FStandard read-only
111110XX0xF80-0xFBFStandard read-only
111111XX0xFC0-0xFFFCustom read-only
  • RISC-V CSR 주소 범위 할당 표

  • 현재 할당된 RISC-V unprevileged CSR 주소
    • 0x001 (URW): fflags — Floating-Point Accured Exceptions.
    • 0x002 (URW): frm — Floating-Point Dynamic Rounding Mode.
    • 0x003 (URW): fcsr — Floating-Point Control and Status Register (frm + fflags).
    • 0xC00 (URO): cycle — Cycle counter for RDCYCLE instruction.
    • 0xC01 (URO): time — Timer for RDTIME instruction.
    • 0xC02 (URO): instret — Instructions-retired counter for RDINSTRET instruction.
    • 0xC03-0xC1F (URO): hpmcounter3 ... hpmcounter31 — Performance-monitoring counter.
    • 0xC80 (URO): cycleh — Upper 32 bits of cycle, RV32 only.
    • 0xC81 (URO): timeh — Upper 32 bits of time, RV32 only.
    • 0xC82 (URO): instreth — Upper 32 bits of instret, RV32 only.
    • 0xC83-0xC9F (URO): hpmcounter3h ... hpmcounter31h — Upper 32 bits of hpmcounter, RV32 only.
  • 현재 할당된 RISC-V supervisor-level CSR 주소
  • 현재 할당된 RISC-V hypervisor 및 VS CSR 주소
  • 현재 할당된 RISC-V machine-level CSR 주소
    • 머신 정보 레지스터
- 0xF11 (MRO): mvendorid — Vendor ID.
- 0xF12 (MRO): marchid — Architecture ID.
- 0xF13 (MRO): mimpid — Implementation ID.
- 0xF14 (MRO): mhartid — Hardware thread ID.
- 0xF15 (MRO): mconfigptr — Pointer to configuration data structure.
  • Machine Trap Setup
  • Machine Trap Handling
  • Machine Configuration
  • Machine Memory Protection
  • Machine Counter/Timers
  • Machine Counter Setup
  • Debug/Trace Registers (shared with Debug Mode)
  • Debug Mode Registers
[각주]

2. 명령어 목록[편집]


2.1. RV32I[편집]

총 40개의 명령어로 구성되어 있다.

2.1.1. ALU 레지스터-상수 연산 명령어[편집]

명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
ADDIaddi rd, rs1, immI-type00000100
SLTIslti rd, rs1, immI-type01000100
SLTIUsltiu rd, rs1, immI-type01100100
XORIxori rd, rs1, immI-type10000100
ORIori rd, rs1, immI-type11000100
ANDIandi rd, rs1, immI-type11100100
LUIlui rd, imm20U-type-01101
AUIPCauipc rd, imm20U-type-00101
NOP 연산은 ADDI x0, x0, 0으로 인코딩된다.
[각주]

2.1.2. Shift immediate 명령어[편집]

명령어mnemonic인코딩imm[11:5]funct3inst[6:5]inst[4:2]
SLLIslli rd, rs1, shamtI-type000000000100100
SRLIsrli rd, rs1, shamtI-type000000010100100
SRAIsrai rd, rs1, shamtI-type010000010100100
32-bit shift immediate 명령어는 immediate의 하위 5비트인 imm[4:0]을 shamt로 사용한다.
[각주]

2.1.3. 레지스터-레지스터 연산 명령어[편집]

명령어mnemonic인코딩funct7funct3inst[6:5]inst[4:2]
ADDadd rd, rs1, rs2R-type000000000001100
SUBsub rd, rs1, rs2R-type010000000001100
SLTslt rd, rs1, rs2R-type000000001001100
SLTUsltu rd, rs1, rs2R-type000000001101100
XORxor rd, rs1, rs2R-type000000010001100
ORor rd, rs1, rs2R-type000000011001100
ANDand rd, rs1, rs2R-type000000011101100
SLLsll rd, rs1, rs2R-type000000000101100
SRLsrl rd, rs1, rs2R-type000000010101100
SRAsra rd, rs1, rs2R-type010000010101100
[각주]

2.1.4. 제어 및 조건부 분기 명령어[편집]

명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
JALjal rd, offsetJ-type-11011
JALRjalr rd, offset(rs1)I-type00011001
BEQbeq rs1, rs2, offsetB-type00011000
BNEbne rs1, rs2, offsetB-type00111000
BLTblt rs1, rs2, offsetB-type10011000
BGEbge rs1, rs2, offsetB-type10111000
BLTUbltu rs1, rs2, offsetB-type11011000
BGEUbgeu rs1, rs2, offsetB-type11111000
[각주]

2.1.5. Load/Store 명령어[편집]

명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
LBlb rd, offset(rs1)I-type00000000
LHlh rd, offset(rs1)I-type00100000
LWlw rd, offset(rs1)I-type01000000
LBUlbu rd, offset(rs1)I-type10000000
LHUlhu rd, offset(rs1)I-type10100000
SBsb rs2, offset(rs1)S-type00001000
SHsh rs2, offset(rs1)S-type00101000
SWsw rs2, offset(rs1)S-type01001000
[각주]

2.1.6. 시스템 및 I/O 명령어[편집]

명령어mnemonic인코딩immrs1rdfunct3inst[6:5]inst[4:2]
FENCEfenceI-typefm|pred|succ0000000011
ECALLecallI-type0000000000000000011100
EBREAKebreakI-type0000000000010000011100
[각주]

2.1.6.1. FENCE[편집]
[각주]

2.2. RV64I[편집]

RV64I에서는 RV32I를 바탕으로 레지스터를 64-bit로 확장하였다. 이에 따라 기존 연산은 64-bit로 확장되어 동작한다.

2.2.1. 변경된 명령어[편집]


2.2.1.1. Shift immediate 명령어[편집]
명령어mnemonic인코딩imm[11:6]funct3inst[6:5]inst[4:2]
SLLIslli rd, rs1, shamtI-type00000000100100
SRLIsrli rd, rs1, shamtI-type00000010100100
SRAIsrai rd, rs1, shamtI-type01000010100100
64-bit shift immediate 명령어는 immediate의 하위 6비트인 imm[5:0]을 shamt로 사용한다.
[각주]

2.2.2. 추가된 명령어[편집]


2.2.2.1. Load/Store 명령어[편집]
명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
LDld rd, offset(rs1)I-type01100000
LWUlwu rd, offset(rs1)I-type11000000
SDsd rs2, offset(rs1)S-type01101000
[각주]

2.2.2.2. 32-bit ALU 레지스터-상수 연산 명령어[편집]
명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
ADDIWaddiw rd, rs1, immI-type00000110
[각주]

2.2.2.3. 32-bit shift immediate 명령어[편집]
명령어mnemonic인코딩imm[11:5]funct3inst[6:5]inst[4:2]
SLLIWslliw rd, rs1, shamtI-type000000000100110
SRLIWsrliw rd, rs1, shamtI-type000000010100110
SRAIWsraiw rd, rs1, shamtI-type010000010100110
32-bit shift immediate 명령어는 immediate의 하위 5비트인 imm[4:0]을 shamt로 사용한다.
[각주]

2.2.2.4. 32-bit 레지스터-레지스터 연산 명령어[편집]
명령어mnemonic인코딩funct7funct3inst[6:5]inst[4:2]
ADDWaddw rd, rs1, rs2R-type000000000001110
SUBWsubw rd, rs1, rs2R-type010000000001110
SLLWsllw rd, rs1, rs2R-type000000000101110
SRLWsrlw rd, rs1, rs2R-type000000010101110
SRAWsraw rd, rs1, rs2R-type010000010101110
[각주]

2.3. "Zifencei" 확장[편집]

명령어mnemonic인코딩immrs1rdfunct3inst[6:5]inst[4:2]
FENCE.Ifence.iI-type00000100011
[각주]

2.4. "Zicsr" 확장[편집]

명령어mnemonic인코딩immrs1funct3inst[6:5]inst[4:2]
CSRRWcsrrw rd, csr, rs1I-typecsrsource00111100
CSRRScsrrs rd, csr, rs1I-typecsrsource01011100
CSRRCcsrrc rd, csr, rs1I-typecsrsource01111100
CSRRWIcsrrwi rd, csr, uimmI-typecsruimm[4:0]10111100
CSRRSIcsrrsi rd, csr, uimmI-typecsruimm[4:0]11011100
CSRRCIcsrrci rd, csr, uimmI-typecsruimm[4:0]11111100
[각주]

2.5. "M" 확장[편집]


2.5.1. RV32M[편집]

명령어mnemonic인코딩funct7funct3inst[6:5]inst[4:2]
MULmul rd, rs1, rs2R-type000000100001100
MULHmulh rd, rs1, rs2R-type000000100101100
MULHSUmulhsu rd, rs1, rs2R-type000000101001100
MULHUmulhu rd, rs1, rs2R-type000000101101100
DIVdiv rd, rs1, rs2R-type000000110001100
DIVUdivu rd, rs1, rs2R-type000000110101100
REMrem rd, rs1, rs2R-type000000111001100
REMUremu rd, rs1, rs2R-type000000111101100
[각주]

2.5.2. RV64M[편집]

명령어mnemonic인코딩funct7funct3inst[6:5]inst[4:2]
MULWmulw rd, rs1, rs2R-type000000100001110
DIVWdivw rd, rs1, rs2R-type000000110001110
DIVUWdivuw rd, rs1, rs2R-type000000110101110
REMWremw rd, rs1, rs2R-type000000111001110
REMUWremuw rd, rs1, rs2R-type000000111101110
[각주]

2.5.3. Zmmul 확장[편집]

Zmmul 확장은 "M" 확장의 곱셈 명령어만 구현한 부분집합이다. (MUL, MULH, MULHU, MULHSU, [RV64 한정] MULW)
[각주]

2.6. "A" 확장[편집]


2.6.1. RV32A[편집]

명령어mnemonic인코딩rs2funct5funct3inst[6:5]inst[4:2]
LR.Wlr.w rd, (rs1)R-type00001001001011
SC.Wsc.w rd, rs2, (rs1)R-typesrc0001101001011
AMOADD.Wamoadd.w rd, rs2, (rs1)R-typesrc0000001001011
AMOSWAP.Wamoswap.w rd, rs2, (rs1)R-typesrc0000101001011
AMOXOR.Wamoxor.w rd, rs2, (rs1)R-typesrc0010001001011
AMOOR.Wamoor.w rd, rs2, (rs1)R-typesrc0100001001011
AMOAND.Wamoand.w rd, rs2, (rs1)R-typesrc0110001001011
AMOMIN.Wamomin.w rd, rs2, (rs1)R-typesrc1000001001011
AMOMAX.Wamomax.w rd, rs2, (rs1)R-typesrc1010001001011
AMOMINU.Wamominu.w rd, rs2, (rs1)R-typesrc1100001001011
AMOMAXU.Wamomaxu.w rd, rs2, (rs1)R-typesrc1110001001011
[각주]

2.6.2. RV64A[편집]

명령어mnemonic인코딩rs2funct5funct3inst[6:5]inst[4:2]
LR.Dlr.d rd, (rs1)R-type00001001101011
SC.Dsc.d rd, rs2, (rs1)R-typesrc0001101101011
AMOADD.Damoadd.d rd, rs2, (rs1)R-typesrc0000001101011
AMOSWAP.Damoswap.d rd, rs2, (rs1)R-typesrc0000101101011
AMOXOR.Damoxor.d rd, rs2, (rs1)R-typesrc0010001101011
AMOOR.Damoor.d rd, rs2, (rs1)R-typesrc0100001101011
AMOAND.Damoand.d rd, rs2, (rs1)R-typesrc0110001101011
AMOMIN.Damomin.d rd, rs2, (rs1)R-typesrc1000001101011
AMOMAX.Damomax.d rd, rs2, (rs1)R-typesrc1010001101011
AMOMINU.Damominu.d rd, rs2, (rs1)R-typesrc1100001101011
AMOMAXU.Damomaxu.d rd, rs2, (rs1)R-typesrc1110001101011
[각주]

2.7. "F" 확장[편집]


2.7.1. RV32F Load/Store 명령어[편집]

명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
FLWflw rd, offset(rs1)I-type01000001
FSWfsw rs2, offset(rs1)S-type01001001
[각주]

2.7.2. RV32F 연산 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FMADD.Sfmadd.s rd, rs1, rs2, rs3R4-typesrc2rs300rm10000
FMSUB.Sfmsub.s rd, rs1, rs2, rs3R4-typesrc2rs300rm10001
FNMSUB.Sfnmsub.s rd, rs1, rs2, rs3R4-typesrc2rs300rm10010
FNMADD.Sfnmadd.s rd, rs1, rs2, rs3R4-typesrc2rs300rm10011
FADD.Sfadd.s rd, rs1, rs2R-typesrc20000000rm10100
FSUB.Sfsub.s rd, rs1, rs2R-typesrc20000100rm10100
FMUL.Sfmul.s rd, rs1, rs2R-typesrc20001000rm10100
FDIV.Sfdiv.s rd, rs1, rs2R-typesrc20001100rm10100
FSQRT.Sfsqrt.s rd, rs1R-type00101100rm10100
FMIN.Sfmin.s rd, rs1, rs2R-typesrc2001010000010100
FMAX.Sfmax.s rd, rs1, rs2R-typesrc2001010000110100
[각주]

2.7.3. RV32F 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.W.Sfcvt.w.s rd, rs1R-type000001100000rm10100
FCVT.WU.Sfcvt.wu.s rd, rs1R-type000011100000rm10100
FCVT.S.Wfcvt.s.w rd, rs1R-type000001101000rm10100
FCVT.S.WUfcvt.s.wu rd, rs1R-type000011101000rm10100
[각주]

2.7.4. RV32F 이동 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FSGNJ.Sfsgnj.s rd, rs1, rs2R-typesrc2001000000010100
FSGNJN.Sfsgnjn.s rd, rs1, rs2R-typesrc2001000000110100
FSGNJX.Sfsgnjx.s rd, rs1, rs2R-typesrc2001000001010100
FMV.X.Wfmv.x.w rd, rs1R-type0111000000010100
FMV.W.Xfmv.w.x rd, rs1R-type0111100000010100
[각주]

2.7.5. RV32F 비교 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FEQ.Sfeq.s rd, rs1, rs2R-typesrc2101000001010100
FLT.Sflt.s rd, rs1, rs2R-typesrc2101000000110100
FLE.Sfle.s rd, rs1, rs2R-typesrc2101000000010100
FCLASS.Sfclass.s rd, rs1R-type0101000000110100
[각주]

2.7.6. RV64F 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.L.Sfcvt.l.s rd, rs1R-type000101100000rm10100
FCVT.LU.Sfcvt.lu.s rd, rs1R-type000111100000rm10100
FCVT.S.Lfcvt.s.l rd, rs1R-type000101101000rm10100
FCVT.S.LUfcvt.s.lu rd, rs1R-type000111101000rm10100
[각주]

2.8. "D" 확장[편집]


2.8.1. RV32D Load/Store 명령어[편집]

명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
FLDfld rd, offset(rs1)I-type01100001
FSDfsd rs2, offset(rs1)S-type01101001
[각주]

2.8.2. RV32D 연산 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FMADD.Dfmadd.d rd, rs1, rs2, rs3R4-typesrc2rs301rm10000
FMSUB.Dfmsub.d rd, rs1, rs2, rs3R4-typesrc2rs301rm10001
FNMSUB.Dfnmsub.d rd, rs1, rs2, rs3R4-typesrc2rs301rm10010
FNMADD.Dfnmadd.d rd, rs1, rs2, rs3R4-typesrc2rs301rm10011
FADD.Dfadd.d rd, rs1, rs2R-typesrc20000001rm10100
FSUB.Dfsub.d rd, rs1, rs2R-typesrc20000101rm10100
FMUL.Dfmul.d rd, rs1, rs2R-typesrc20001001rm10100
FDIV.Dfdiv.d rd, rs1, rs2R-typesrc20001101rm10100
FSQRT.Dfsqrt.d rd, rs1R-type00101101rm10100
FMIN.Dfmin.d rd, rs1, rs2R-typesrc2001010100010100
FMAX.Dfmax.d rd, rs1, rs2R-typesrc2001010100110100
[각주]

2.8.3. RV32D 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.D.Sfcvt.d.s rd, rs1R-type000000100001rm10100
FCVT.S.Dfcvt.s.d rd, rs1R-type000010100000rm10100
FCVT.W.Dfcvt.w.d rd, rs1R-type000001100001rm10100
FCVT.WU.Dfcvt.wu.d rd, rs1R-type000011100001rm10100
FCVT.D.Wfcvt.d.w rd, rs1R-type000001101001rm10100
FCVT.D.WUfcvt.d.wu rd, rs1R-type000011101001rm10100
[각주]

2.8.4. RV32D 이동 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FSGNJ.Dfsgnj.d rd, rs1, rs2R-typesrc2001000100010100
FSGNJN.Dfsgnjn.d rd, rs1, rs2R-typesrc2001000100110100
FSGNJX.Dfsgnjx.d rd, rs1, rs2R-typesrc2001000101010100
[각주]

2.8.5. RV32D 비교 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FEQ.Dfeq.d rd, rs1, rs2R-typesrc2101000101010100
FLT.Dflt.d rd, rs1, rs2R-typesrc2101000100110100
FLE.Dfle.d rd, rs1, rs2R-typesrc2101000100010100
FCLASS.Dfclass.d rd, rs1R-type0101000100110100
[각주]

2.8.6. RV64D 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.L.Dfcvt.l.d rd, rs1R-type000101100001rm10100
FCVT.LU.Dfcvt.lu.d rd, rs1R-type000111100001rm10100
FCVT.D.Lfcvt.d.l rd, rs1R-type000101101001rm10100
FCVT.D.LUfcvt.d.lu rd, rs1R-type000111101001rm10100
[각주]

2.8.7. RV64D 이동 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FMV.X.Dfmv.x.d rd, rs1R-type0111000100010100
FMV.D.Xfmv.d.x rd, rs1R-type0111100100010100
[각주]

2.9. "Q" 확장[편집]


2.9.1. RV32Q Load/Store 명령어[편집]

명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
FLQflq rd, offset(rs1)I-type10000001
FSQfsq rs2, offset(rs1)S-type10001001
[각주]

2.9.2. RV32Q 연산 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FMADD.Qfmadd.q rd, rs1, rs2, rs3R4-typesrc2rs311rm10000
FMSUB.Qfmsub.q rd, rs1, rs2, rs3R4-typesrc2rs311rm10001
FNMSUB.Qfnmsub.q rd, rs1, rs2, rs3R4-typesrc2rs311rm10010
FNMADD.Qfnmadd.q rd, rs1, rs2, rs3R4-typesrc2rs311rm10011
FADD.Qfadd.q rd, rs1, rs2R-typesrc20000011rm10100
FSUB.Qfsub.q rd, rs1, rs2R-typesrc20000111rm10100
FMUL.Qfmul.q rd, rs1, rs2R-typesrc20001011rm10100
FDIV.Qfdiv.q rd, rs1, rs2R-typesrc20001111rm10100
FSQRT.Qfsqrt.q rd, rs1R-type00101111rm10100
FMIN.Qfmin.q rd, rs1, rs2R-typesrc2001011100010100
FMAX.Qfmax.q rd, rs1, rs2R-typesrc2001011100110100
[각주]

2.9.3. RV32Q 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.Q.Sfcvt.q.s rd, rs1R-type000000100011rm10100
FCVT.Q.Dfcvt.q.d rd, rs1R-type000010100011rm10100
FCVT.S.Qfcvt.s.q rd, rs1R-type000110100000rm10100
FCVT.D.Qfcvt.d.q rd, rs1R-type000110100001rm10100
FCVT.W.Qfcvt.w.q rd, rs1R-type000001100011rm10100
FCVT.WU.Qfcvt.wu.q rd, rs1R-type000011100011rm10100
FCVT.Q.Wfcvt.q.w rd, rs1R-type000001101011rm10100
FCVT.Q.WUfcvt.q.wu rd, rs1R-type000011101011rm10100
[각주]

2.9.4. RV32Q 이동 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FSGNJ.Qfsgnj.q rd, rs1, rs2R-typesrc2001001100010100
FSGNJN.Qfsgnjn.q rd, rs1, rs2R-typesrc2001001100110100
FSGNJX.Qfsgnjx.q rd, rs1, rs2R-typesrc2001001101010100
[각주]

2.9.5. RV32Q 비교 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FEQ.Qfeq.q rd, rs1, rs2R-typesrc2101001101010100
FLT.Qflt.q rd, rs1, rs2R-typesrc2101001100110100
FLE.Qfle.q rd, rs1, rs2R-typesrc2101001100010100
FCLASS.Qfclass.q rd, rs1R-type0101001100110100
[각주]

2.9.6. RV64Q 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.Q.Lfcvt.q.l rd, rs1R-type000101100011rm10100
FCVT.Q.LUfcvt.q.lu rd, rs1R-type000111100011rm10100
FCVT.L.Qfcvt.l.q rd, rs1R-type000101101011rm10100
FCVT.LU.Qfcvt.lu.q rd, rs1R-type000111101011rm10100
[각주]

2.10. "Zfh", "Zfhmin" 확장[편집]

"Zfhmin" 확장은 Load/Store 명령어 및 변환 명령어만을 포함한다.


2.10.1. RV32Zfh Load/Store 명령어[편집]

명령어mnemonic인코딩funct3inst[6:5]inst[4:2]
FLHflh rd, offset(rs1)I-type00100001
FSHfsh rs2, offset(rs1)S-type00101001
[각주]

2.10.2. RV32Zfh 연산 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FMADD.Hfmadd.h rd, rs1, rs2, rs3R4-typesrc2rs310rm10000
FMSUB.Hfmsub.h rd, rs1, rs2, rs3R4-typesrc2rs310rm10001
FNMSUB.Hfnmsub.h rd, rs1, rs2, rs3R4-typesrc2rs310rm10010
FNMADD.Hfnmadd.h rd, rs1, rs2, rs3R4-typesrc2rs310rm10011
FADD.Hfadd.h rd, rs1, rs2R-typesrc20000010rm10100
FSUB.Hfsub.h rd, rs1, rs2R-typesrc20000110rm10100
FMUL.Hfmul.h rd, rs1, rs2R-typesrc20001010rm10100
FDIV.Hfdiv.h rd, rs1, rs2R-typesrc20001110rm10100
FSQRT.Hfsqrt.h rd, rs1R-type00101110rm10100
FMIN.Hfmin.h rd, rs1, rs2R-typesrc2001011000010100
FMAX.Hfmax.h rd, rs1, rs2R-typesrc2001011000110100
[각주]

2.10.3. RV32Zfh 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.S.Hfcvt.s.h rd, rs1R-type000100100000rm10100
FCVT.D.Hfcvt.d.h rd, rs1R-type000100100001rm10100
FCVT.Q.Hfcvt.d.h rd, rs1R-type000100100001rm10100
FCVT.H.Sfcvt.h.s rd, rs1R-type000000100010rm10100
FCVT.H.Dfcvt.h.d rd, rs1R-type000010100010rm10100
FCVT.H.Qfcvt.h.q rd, rs1R-type000110100010rm10100
FCVT.W.Hfcvt.w.h rd, rs1R-type000001100010rm10100
FCVT.WU.Hfcvt.wu.h rd, rs1R-type000011100010rm10100
FCVT.H.Wfcvt.h.w rd, rs1R-type000001101010rm10100
FCVT.H.WUfcvt.h.wu rd, rs1R-type000011101010rm10100
[각주]

2.10.4. RV32Zfh 이동 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FSGNJ.Hfsgnj.h rd, rs1, rs2R-typesrc2001001000010100
FSGNJN.Hfsgnjn.h rd, rs1, rs2R-typesrc2001001000110100
FSGNJX.Hfsgnjx.h rd, rs1, rs2R-typesrc2001001001010100
FMV.X.Hfmv.x.h rd, rs1R-type0111001000010100
FMV.H.Xfmv.h.x rd, rs1R-type0111101000010100
[각주]

2.10.5. RV32Zfh 비교 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FEQ.Hfeq.h rd, rs1, rs2R-typesrc2101001001010100
FLT.Hflt.h rd, rs1, rs2R-typesrc2101001000110100
FLE.Hfle.h rd, rs1, rs2R-typesrc2101001000010100
FCLASS.Hfclass.h rd, rs1R-type0101001000110100
[각주]

2.10.6. RV64Zfh 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]
FCVT.L.Hfcvt.l.h rd, rs1R-type000101100010rm10100
FCVT.LU.Hfcvt.lu.h rd, rs1R-type000111100010rm10100
FCVT.H.Lfcvt.h.l rd, rs1R-type000101101010rm10100
FCVT.H.LUfcvt.h.lu rd, rs1R-type000111101010rm10100
[각주]

2.11. RISC-V Privileged ISA[편집]


2.11.1. Trap-Return 명령어[편집]

명령어mnemonic인코딩rdrs1funct12funct3inst[6:5]inst[4:2]
SRETsretI-type0000010000001000011100
MRETmretI-type0000110000001000011100
[각주]

2.11.2. 인터럽트 관리 명령어[편집]

명령어mnemonic인코딩rdrs1funct12funct3inst[6:5]inst[4:2]
WFIwfiI-type0000010000010100011100
[각주]

2.11.3. 슈퍼바이저 메모리 관리 명령어[편집]

명령어mnemonic인코딩rdrs2rs1funct7funct3inst[6:5]inst[4:2]
SFENCE.VMAsfence.vma rs1, rs2R-type0asidvaddr000100100011100
SINVAL.VMAsinval.vma rs1, rs2R-type0asidvaddr000101100011100
SFENCE.W.INVALsfence.w.invalR-type000000110000011100
SFENCE.INVAL.IRsfence.inval.irR-type010000110000011100
[각주]

2.11.4. 하이퍼바이저 메모리 관리 명령어[편집]

명령어mnemonic인코딩rdrs2rs1funct7funct3inst[6:5]inst[4:2]
HFENCE.VVMAhfence.vvma rs1, rs2R-type0asidvaddr001000100011100
HFENCE.GVMAhfence.gvma rs1, rs2R-type0vmidgaddr011000100011100
HINVAL.VVMAhinval.vvma rs1, rs2R-type0asidvaddr001001100011100
HINVAL.GVMAhinval.gvma rs1, rs2R-type0vmidgaddr011001100011100
[각주]

2.11.5. 하이퍼바이저 가상머신 Load/Store 명령어[편집]

명령어mnemonic인코딩rdrs2funct7funct3inst[6:5]inst[4:2]
HLV.Bhlv.b rd, (rs1)R-typerd00000011000010011100
HLV.BUhlv.bu rd, (rs1)R-typerd00001011000010011100
HLV.Hhlv.h rd, (rs1)R-typerd00000011001010011100
HLV.HUhlv.hu rd, (rs1)R-typerd00001011001010011100
HLVX.HUhlvx.hu rd, (rs1)R-typerd00011011001010011100
HLV.Whlv.w rd, (rs1)R-typerd00000011010010011100
HLVX.WUhlvx.wu rd, (rs1)R-typerd00011011010010011100
HSV.Bhsv.b rs2, (rs1)R-type0rs2011000110011100
HSV.Hhsv.h rs2, (rs1)R-type0rs2011001110011100
HSV.Whsv.w rs2, (rs1)R-type0rs2011010110011100
[각주]

2.11.5.1. RV64[편집]
명령어mnemonic인코딩rdrs2funct7funct3inst[6:5]inst[4:2]
HLV.WUhlv.wu rd, (rs1)R-typerd00001011010010011100
HLV.Dhlv.d rd, (rs1)R-typerd00000011011010011100
HSV.Dhsv.d rs2, (rs1)R-type0rs2011011110011100
[각주]

2.12. "C" 확장[편집]


2.12.1. 스택 포인터 기반 Load/Store 명령어[편집]

명령어mnemonic인코딩funct3inst[12]inst[11:7]inst[6:2]op비고
C.LWSPc.lwsp rd, offset(sp)CI-type010offset[5]rdoffset[4:2|7:6]10[4]
C.LDSPc.ldsp rd, offset(sp)CI-type011offset[5]rdoffset[4:3|8:6]10[5]
C.LQSPc.lqsp rd, offset(sp)CI-type001offset[5]rdoffset[4|9:6]10[6]
C.FLWSPc.flwsp rd, offset(sp)CI-type011offset[5]rdoffset[4:2|7:6]10[7]
C.FLDSPc.fldsp rd, offset(sp)CI-type001offset[5]rdoffset[4:3|8:6]10[8]
C.SWSPc.swsp rs2, offset(sp)CSS-type110offset[5:2|7:6]rs210[9]
C.SDSPc.sdsp rs2, offset(sp)CSS-type111offset[5:3|8:6]rs210[10]
C.SQSPc.sqsp rs2, offset(sp)CSS-type101offset[5:4|9:6]rs210[11]
C.FSWSPc.fswsp rs2, offset(sp)CSS-type111offset[5:2|7:6]rs210[12]
C.FSDSPc.fsdsp rs2, offset(sp)CSS-type101offset[5:3|8:6]rs210[13]
[4] lw rd, offset(sp)로 확장된다.[5] RV64C/RV128C only. ld rd, offset(sp)로 확장된다.[6] RV128C only. lq rd, offset(sp)로 확장된다.[7] RV32FC only.[8] RV32DC/RV64DC only.[9] sw rs2, offset(sp)로 확장된다.[10] RV64C/RV128C only. sd rs2, offset(sp)로 확장된다.[11] RV128C only. sq rs2, offset(sp)로 확장된다.[12] RV32FC only.[13] RV32DC/RV64DC only.


2.12.2. 레지스터 기반 Load/Store 명령어[편집]

명령어mnemonic인코딩funct3inst[12:10]inst[9:7]inst[6:5]inst[4:2]op비고
C.LWc.lw rd', offset(rs1')CL-type010offset[5:3]rs1'offset[2|6]rd'00[14]
C.LDc.ld rd', offset(rs1')CL-type011offset[5:3]rs1'offset[7:6]rd'00[15]
C.LQc.lq rd', offset(rs1')CL-type001offset[5:4|8]rs1'offset[7:6]rd'00[16]
C.FLWc.flw rd', offset(rs1')CL-type011offset[5:3]rs1'offset[2|6]rd'00[17]
C.FLDc.fld rd', offset(rs1')CL-type001offset[5:3]rs1'offset[7:6]rd'00[18]
C.SWc.sw rs2', offset(rs1')CS-type110offset[5:3]rs1'offset[2|6]rs2'00[19]
C.SDc.sd rs2', offset(rs1')CS-type111offset[5:3]rs1'offset[7:6]rs2'00[20]
C.SQc.sq rs2', offset(rs1')CS-type101offset[5:4|8]rs1'offset[7:6]rs2'00[21]
C.FSWc.fsw rs2', offset(rs1')CS-type111offset[5:3]rs1'offset[2|6]rs2'00[22]
C.FSDc.fsd rs2', offset(rs1')CS-type101offset[5:3]rs1'offset[7:6]rs2'00[23]
[14] lw rd', offset(rs1')로 확장된다.[15] RV64C/RV128C only. ld rd', offset(rs1')로 확장된다.[16] RV128C only. lq rd', offset(rs1')로 확장된다.[17] RV32FC only.[18] RV32DC/RV64DC only.[19] sw rs2', offset(rs1')로 확장된다.[20] RV64C/RV128C only. sd rs2', offset(rs1')로 확장된다.[21] RV128C only. sq rs2', offset(rs1')로 확장된다.[22] RV32FC only.[23] RV32DC/RV64DC only.


2.12.3. 제어 및 조건부 분기 명령어[편집]

명령어mnemonic인코딩funct3inst[12]inst[11:10]inst[9:7]inst[6:5]inst[4:2]op비고
C.Jc.j offsetCJ-type101offset[11|4|9:8|10|6|7|3:1|5]01[24]
C.JALc.jal offsetCJ-type001offset[11|4|9:8|10|6|7|3:1|5]01[25]
C.JRc.jr offset(rs1)CR-type1000rs1≠0010[26]
C.JALRc.jalr offset(rs1)CR-type1001rs1≠0010[27]
C.BEQZc.beqz offsetCB-type110offset[8|4:3]rs1'offset[7:6|2:1|5]01[28]
C.BNEZc.bnez offsetCB-type111offset[8|4:3]rs1'offset[7:6|2:1|5]01[29]
[24] jal x0, offset으로 확장된다.[25] RV32C only. jal ra, offset으로 확장된다.[26] jalr x0, 0(rs1)로 확장된다.[27] jalr ra, 0(rs1)로 확장된다.[28] beq rs1', x0, offset으로 확장된다.[29] bne rs1', x0, offset으로 확장된다.


2.12.4. 상수 생성 명령어[편집]

명령어mnemonic인코딩funct3inst[12]inst[11:7]inst[6:2]op비고
C.LIc.li rd, immCI-type010imm[5]rd≠0imm[4:0]01[30]
C.LUIc.lui rd, nzimmCI-type011nzimm[17]rd≠{0,2}nzimm[16:12]01[31]
[30] addi rd, x0, imm으로 확장된다.[31] lui rd, nzimm으로 확장된다.


2.12.5. 레지스터-상수 명령어[편집]

명령어mnemonic인코딩funct3inst[12][11:10][9:7]inst[6:5]inst[4:2]op비고
C.ADDIc.addi rd, nzimmCI-type000nzimm[5]rd/rs1nzimm[4:0]01[32]
C.ADDIWc.addiw rd, immCI-type001imm[5]rd/rs1≠0imm[4:0]01[33]
C.ADDI4SPNc.addi4spn rd, nzuimmCIW-type000nzuimm[5:4|9:6|2|3]rd'00[34]
C.ADDI16SPc.addi16sp rd, nzimmCI-type011nzimm[9]2nzimm[4|6|8:7|5]01[35]
C.SLLIc.slli rd, shamtCI-type000shamt[5]rd/rs1shamt[4:0]10[36]
C.SRLIc.srli rd', shamtCI-type100shamt[5]00rd'/rs1'shamt[4:0]01[37]
C.SRAIc.srai rd', shamtCI-type100shamt[5]01rd'/rs1'shamt[4:0]01[38]
C.ANDIc.andi rd', immCI-type100imm[5]10rd'/rs1'imm[4:0]01[39]
NOP 연산은 C.ADDI x0, 0으로 인코딩된다. C.ADDI에서 rd=0, nzimm≠0 또는 rd≠0, nzimm=0인 경우는 HINT 명령어를 인코딩하는 데 사용된다.
[32] addi rd, rd, nzimm으로 확장된다.[33] RV64C/RV128C only. addiw rd, rd, imm으로 확장된다.[34] addi rd', sp, nzuimm으로 확장된다.[35] addi sp, sp, nzimm으로 확장된다.[36] slli rd, rd, shamt로 확장된다. 단, RV128C에서 shamt=0은 slli rd, rd, 64를 의미한다. (C.SLLI64)[37] srli rd', rd', shamt로 확장된다. 단, RV128C에서 shamt=0은 srli rd, rd, 64를 의미한다. (C.SRLI64)[38] srai rd', rd', shamt로 확장된다. 단, RV128C에서 shamt=0은 srai rd, rd, 64를 의미한다. (C.SRAI64)[39] andi rd', rd', imm으로 확장된다.


2.12.6. 레지스터-레지스터 명령어[편집]

명령어mnemonic인코딩funct4inst[11:10][9:7]inst[6:5][4:2]op비고
C.MVc.mv rd, rs2CR-type1000rd≠0rs2≠010[40]
C.ADDc.add rd, rs2CR-type1001rd/rs1≠0rs2≠010[41]
C.SUBc.sub rd', rs2'CA-type100011rd'/rs1'00rs2'01[42]
C.XORc.xor rd', rs2'CA-type100011rd'/rs1'01rs2'01[43]
C.ORc.or rd', rs2'CA-type100011rd'/rs1'10rs2'01[44]
C.ANDc.and rd', rs2'CA-type100011rd'/rs1'11rs2'01[45]
C.ADDWc.addw rd', rs2'CA-type100111rd'/rs1'01rs2'01[46]
C.SUBWc.subw rd', rs2'CA-type100111rd'/rs1'00rs2'01[47]
[40] add rd, x0, rs2로 확장된다.[41] add rd, rd, rs2로 확장된다.[42] sub rd', rd', rs2'로 확장된다.[43] xor rd', rd', rs2'로 확장된다.[44] or rd', rd', rs2'로 확장된다.[45] and rd', rd', rs2'로 확장된다.[46] addw rd', rd', rs2'로 확장된다.[47] subw rd', rd', rs2'로 확장된다.


2.12.7. Breakpoint 명령어[편집]

명령어mnemonic인코딩funct4inst[11:7]inst[6:2]op비고
C.EBREAKc.ebreakCR-type10010010
C.ADD opcode에서 rd=rs2=0인 경우는 C.EBREAK 명령어를 인코딩하는 데 사용된다.
[각주]

2.12.8. Illegal 명령어[편집]

명령어mnemonic인코딩funct3inst[12]inst[11:7]inst[6:2]op비고
Illegal-CI-type00000000
[각주]

2.13. "Zam" 확장[편집]

[각주]

2.14. "Zihintl" 확장[편집]

[각주]

2.15. "Zihintpause" 확장[편집]

[각주]

2.16. "Zfinx" / "Zdinx" / "Zhinx " / "Zhinxmin" 확장[편집]

[각주]

2.17. "Zfa" 확장[편집]


2.17.1. 상수 생성 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]비고
FLI.fmtR-type111110fmt00010100
FLI.Sfli.s rd, rs1R-type1111100000010100
FLI.Dfli.d rd, rs1R-type1111100100010100
FLI.Hfli.h rd, rs1R-type1111101000010100
FLI.Qfli.q rd, rs1R-type1111101100010100
[각주]

2.17.2. 최대/최소 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]비고
FMINM.Sfminm.s rd, rs1, rs2R-typesrc2001010001010100
FMINM.Dfminm.d rd, rs1, rs2R-typesrc2001010101010100
FMINM.Hfminm.h rd, rs1, rs2R-typesrc2001011001010100
FMINM.Qfminm.q rd, rs1, rs2R-typesrc2001011101010100
FMAXM.Sfmaxm.s rd, rs1, rs2R-typesrc2001010001110100
FMAXM.Dfmaxm.d rd, rs1, rs2R-typesrc2001010101110100
FMAXM.Hfmaxm.h rd, rs1, rs2R-typesrc2001011001110100
FMAXM.Qfmaxm.q rd, rs1, rs2R-typesrc2001011101110100
[각주]

2.17.3. 정수 반올림 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]비고
FROUND.Sfround.s rd, rs1R-type001000100000rm10100
FROUNDNX.Sfroundnx.s rd, rs1R-type001010100000rm10100
FROUND.Dfround.d rd, rs1R-type001000100001rm10100
FROUNDNX.Dfroundnx.d rd, rs1R-type001010100001rm10100
FROUND.Hfround.h rd, rs1R-type001000100010rm10100
FROUNDNX.Hfroundnx.h rd, rs1R-type001010100010rm10100
FROUND.Qfround.q rd, rs1R-type001000100011rm10100
FROUNDNX.Qfroundnx.q rd, rs1R-type001010100011rm10100
[각주]

2.17.4. 모듈러 정수 변환 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]비고
FCVTMOD.W.Dfcvtmod.w.d rd, rs1R-type01000110000100110100[48]
[48] "D" 확장 한정


2.17.5. 이동 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]비고
FMVH.X.Dfmvh.x.d rd, rs1R-type1111000100010100[49]
FMVP.D.Xfmvp.d.x rd, rs1, rs2R-typers2101100100010100[50]
FMVH.X.Qfmvh.x.q rd, rs1R-type1111001100010100[51]
FMVP.Q.Xfmvp.q.x rd, rs1, rs2R-typers2101101100010100[52]
[49] RV32D 한정.[50] RV32D 한정.[51] RV64Q 한정.[52] RV64Q 한정.


2.17.6. 비교 명령어[편집]

명령어mnemonic인코딩rs2funct5fmtfunct3inst[6:5]inst[4:2]비고
FLEQ.Sfleq.s rd, rs1, rs2R-typesrc2101000010010100
FLTQ.Sfltq.s rd, rs1, rs2R-typesrc2101000010110100
FLEQ.Dfleq.d rd, rs1, rs2R-typesrc2101000110010100
FLTQ.Dfltq.d rd, rs1, rs2R-typesrc2101000110110100
FLEQ.Hfleq.h rd, rs1, rs2R-typesrc2101001010010100
FLTQ.Hfltq.h rd, rs1, rs2R-typesrc2101001010110100
FLEQ.Qfleq.q rd, rs1, rs2R-typesrc2101001110010100
FLTQ.Qfltq.q rd, rs1, rs2R-typesrc2101001110110100
[각주]

2.18. "B" 확장[편집]

[각주]

2.19. "P" 확장[편집]

[각주]

2.20. "V" 확장[편집]


2.20.1. 벡터 Load/Store 명령어[편집]


2.20.1.1. Unit-Stride Load/Store 명령어[편집]
명령어mnemonic인코딩nfmewmopvmlumopwidthinst[6:5]inst[4:2]비고
VLE8.Vvle8.v vd, (rs1), vmVL*000000vm0000000000001[vm]
VLE16.Vvle16.v vd, (rs1), vmVL*000000vm0000010100001[vm]
VLE32.Vvle32.v vd, (rs1), vmVL*000000vm0000011000001[vm]
VLE64.Vvle64.v vd, (rs1), vmVL*000000vm0000011100001[vm]
VLM.Vvlm.v vd, (rs1)VL*00000010101100000001
VLE8FF.Vvle8ff.v vd, (rs1), vmVL*000000vm1000000000001[vm]
VLE16FF.Vvle16ff.v vd, (rs1), vmVL*000000vm1000010100001[vm]
VLE32FF.Vvle32ff.v vd, (rs1), vmVL*000000vm1000011000001[vm]
VLE64FF.Vvle64ff.v vd, (rs1), vmVL*000000vm1000011100001[vm]
VSE8.Vvse8.v vs3, (rs1), vmVS*000000vm0000000001001[vm]
VSE16.Vvse16.v vs3, (rs1), vmVS*000000vm0000010101001[vm]
VSE32.Vvse32.v vs3, (rs1), vmVS*000000vm0000011001001[vm]
VSE64.Vvse64.v vs3, (rs1), vmVS*000000vm0000011101001[vm]
VSM.Vvsm.v vs3, (rs1)VS*00000010101100001001
VSE8FF.Vvse8ff.v vs3, (rs1), vmVS*000000vm1000000001001[vm]
VSE16FF.Vvse16ff.v vs3, (rs1), vmVS*000000vm1000010101001[vm]
VSE32FF.Vvse32ff.v vs3, (rs1), vmVS*000000vm1000011001001[vm]
VSE64FF.Vvse64ff.v vs3, (rs1), vmVS*000000vm1000011101001[vm]
[vm] A B C D E F G H I J K L M N O P vm 필드는 생략하거나 v0.t로 둘 수 있다. vm=0인 경우 v0.mask\[i\] 값을 사용하고 vm=1인 경우 unmasked.


2.20.1.2. Strided Load/Store 명령어[편집]
명령어mnemonic인코딩nfmewmopvmlumopwidthinst[6:5]inst[4:2]비고
VLSE8.Vvlse8.v vd, (rs1), rs2, vmVLS*000010vm-00000001[vm]
VLSE16.Vvlse16.v vd, (rs1), rs2, vmVLS*000010vm-10100001[vm]
VLSE32.Vvlse32.v vd, (rs1), rs2, vmVLS*000010vm-11000001[vm]
VLSE64.Vvlse64.v vd, (rs1), rs2, vmVLS*000010vm-11100001[vm]
VSSE8.Vvsse8.v vs3, (rs1), rs2, vmVSS*000010vm-00001001[vm]
VSSE16.Vvsse16.v vs3, (rs1), rs2, vmVSS*000010vm-10101001[vm]
VSSE32.Vvsse32.v vs3, (rs1), rs2, vmVSS*000010vm-11001001[vm]
VSSE64.Vvsse64.v vs3, (rs1), rs2, vmVSS*000010vm-11101001[vm]
[vm] A B C D E F G H vm 필드는 생략하거나 v0.t로 둘 수 있다. vm=0인 경우 v0.mask\[i\] 값을 사용하고 vm=1인 경우 unmasked.


2.20.1.3. Vector Indexed Load/Store 명령어[편집]
명령어mnemonic인코딩nfmewmopvmlumopwidthinst[6:5]inst[4:2]비고
VLUXEI8.Vvluxei8.v vd, (rs1), vs2, vmVLX*000001vm-00000001[vm]
VLUXEI16.Vvluxei16.v vd, (rs1), vs2, vmVLX*000001vm-10100001[vm]
VLUXEI32.Vvluxei32.v vd, (rs1), vs2, vmVLX*000001vm-11000001[vm]
VLUXEI64.Vvluxei64.v vd, (rs1), vs2, vmVLX*000001vm-11100001[vm]
VLOXEI8.Vvloxei8.v vd, (rs1), vs2, vmVLX*000011vm-00000001[vm]
VLOXEI16.Vvloxei16.v vd, (rs1), vs2, vmVLX*000011vm-10100001[vm]
VLOXEI32.Vvloxei32.v vd, (rs1), vs2, vmVLX*000011vm-11000001[vm]
VLOXEI64.Vvloxei64.v vd, (rs1), vs2, vmVLX*000011vm-11100001[vm]
VSUXEI8.Vvsuxei8.v vs3, (rs1), vs2, vmVSX*000001vm-00001001[vm]
VSUXEI16.Vvsuxei16.v vs3, (rs1), vs2, vmVSX*000001vm-10101001[vm]
VSUXEI32.Vvsuxei32.v vs3, (rs1), vs2, vmVSX*000001vm-11001001[vm]
VSUXEI64.Vvsuxei64.v vs3, (rs1), vs2, vmVSX*000001vm-11101001[vm]
VSOXEI8.Vvsoxei8.v vs3, (rs1), vs2, vmVSX*000011vm-00001001[vm]
VSOXEI16.Vvsoxei16.v vs3, (rs1), vs2, vmVSX*000011vm-10101001[vm]
VSOXEI32.Vvsoxei32.v vs3, (rs1), vs2, vmVSX*000011vm-11001001[vm]
VSOXEI64.Vvsoxei64.v vs3, (rs1), vs2, vmVSX*000011vm-11101001[vm]
[vm] A B C D E F G H I J K L M N O P vm 필드는 생략하거나 v0.t로 둘 수 있다. vm=0인 경우 v0.mask\[i\] 값을 사용하고 vm=1인 경우 unmasked.


2.20.1.4. Unit-Stride Segment Load/Store 명령어[편집]
명령어mnemonic인코딩nfmewmopvmlumopwidthinst[6:5]inst[4:2]비고
VLSEG<nf>E8.Vvlseg<nf>e8.v vd, (rs1), vmVL*nf000vm0000000000001[vm]
VLSEG<nf>E16.Vvlseg<nf>e16.v vd, (rs1), vmVL*nf000vm0000010100001[vm]
VLSEG<nf>E32.Vvlseg<nf>e32.v vd, (rs1), vmVL*nf000vm0000011000001[vm]
VLSEG<nf>E64.Vvlseg<nf>e64.v vd, (rs1), vmVL*nf000vm0000011100001[vm]
VLSEG<nf>E8FF.Vvlseg<nf>e8ff.v vd, (rs1), vmVL*nf000vm1000000000001[vm]
VLSEG<nf>E16FF.Vvlseg<nf>e16ff.v vd, (rs1), vmVL*nf000vm1000010100001[vm]
VLSEG<nf>E32FF.Vvlseg<nf>e32ff.v vd, (rs1), vmVL*nf000vm1000011000001[vm]
VLSEG<nf>E64FF.Vvlseg<nf>e64ff.v vd, (rs1), vmVL*nf000vm1000011100001[vm]
VSSEG<nf>E8.Vvsseg<nf>e8.v vs3, (rs1), vmVS*nf000vm0000000001001[vm]
VSSEG<nf>E16.Vvsseg<nf>e16.v vs3, (rs1), vmVS*nf000vm0000010101001[vm]
VSSEG<nf>E32.Vvsseg<nf>e32.v vs3, (rs1), vmVS*nf000vm0000011001001[vm]
VSSEG<nf>E64.Vvsseg<nf>e64.v vs3, (rs1), vmVS*nf000vm0000011101001[vm]
VSSEG<nf>E8FF.Vvsseg<nf>e8ff.v vs3, (rs1), vmVS*nf000vm1000000001001[vm]
VSSEG<nf>E16FF.Vvsseg<nf>e16ff.v vs3, (rs1), vmVS*nf000vm1000010101001[vm]
VSSEG<nf>E32FF.Vvsseg<nf>e32ff.v vs3, (rs1), vmVS*nf000vm1000011001001[vm]
VSSEG<nf>E64FF.Vvsseg<nf>e64ff.v vs3, (rs1), vmVS*nf000vm1000011101001[vm]
[vm] A B C D E F G H I J K L M N O P vm 필드는 생략하거나 v0.t로 둘 수 있다. vm=0인 경우 v0.mask\[i\] 값을 사용하고 vm=1인 경우 unmasked.


2.20.1.5. Strided Segment Load/Store 명령어[편집]
[각주]

2.20.1.6. Vector Indexed Segment Load/Store 명령어[편집]
[각주]

2.20.1.7. 레지스터 단위 Load/Store 명령어[편집]
명령어mnemonic인코딩nfmewmopvmlumopwidthinst[6:5]inst[4:2]비고
VL1RE8.Vvl1re8.v vd, (rs1)VL*00000010100000000001
VL1RE16.Vvl1re16.v vd, (rs1)VL*00000010100010100001
VL1RE32.Vvl1re32.v vd, (rs1)VL*00000010100011000001
VL1RE64.Vvl1re64.v vd, (rs1)VL*00000010100011100001
VL2RE8.Vvl2re8.v vd, (rs1)VL*00100010100000000001
VL2RE16.Vvl2re16.v vd, (rs1)VL*00100010100010100001
VL2RE32.Vvl2re32.v vd, (rs1)VL*00100010100011100001
VL2RE64.Vvl2re64.v vd, (rs1)VL*00100010100011100001
VL4RE8.Vvl4re8.v vd, (rs1)VL*01100010100000000001
VL4RE16.Vvl4re16.v vd, (rs1)VL*01100010100010100001
VL4RE32.Vvl4re32.v vd, (rs1)VL*01100010100011000001
VL4RE64.Vvl4re64.v vd, (rs1)VL*01100010100011100001
VL8RE8.Vvl8re8.v vd, (rs1)VL*11100010100000000001
VL8RE16.Vvl8re16.v vd, (rs1)VL*11100010100010100001
VL8RE32.Vvl8re32.v vd, (rs1)VL*11100010100011000001
VL8RE64.Vvl8re64.v vd, (rs1)VL*11100010100011100001
VS1RE8.Vvs1re8.v vs3, (rs1)VS*00000010100000001001
VS1RE16.Vvs1re16.v vs3, (rs1)VS*00000010100010101001
VS1RE32.Vvs1re32.v vs3, (rs1)VS*00000010100011001001
VS1RE64.Vvs1re64.v vs3, (rs1)VS*00000010100011101001
VS2RE8.Vvs2re8.v vs3, (rs1)VS*00100010100000001001
VS2RE16.Vvs2re16.v vs3, (rs1)VS*00100010100010101001
VS2RE32.Vvs2re32.v vs3, (rs1)VS*00100010100011101001
VS2RE64.Vvs2re64.v vs3, (rs1)VS*00100010100011101001
VS4RE8.Vvs4re8.v vs3, (rs1)VS*01100010100000001001
VS4RE16.Vvs4re16.v vs3, (rs1)VS*01100010100010101001
VS4RE32.Vvs4re32.v vs3, (rs1)VS*01100010100011001001
VS4RE64.Vvs4re64.v vs3, (rs1)VS*01100010100011101001
VS8RE8.Vvs8re8.v vs3, (rs1)VS*11100010100000001001
VS8RE16.Vvs8re16.v vs3, (rs1)VS*11100010100010101001
VS8RE32.Vvs8re32.v vs3, (rs1)VS*11100010100011001001
VS8RE64.Vvs8re64.v vs3, (rs1)VS*11100010100011101001
[각주]

2.20.2. 벡터 정수 연산 명령어[편집]

[각주]

2.20.3. 벡터 고정소수점 연산 명령어[편집]

[각주]

2.20.4. 벡터 부동소수점 연산 명령어[편집]

[각주]

2.20.5. 벡터 Reduction 연산 명령어[편집]

[각주]

2.20.6. 벡터 마스크 연산 명령어[편집]

[각주]

2.20.7. 벡터 Permutation 연산 명령어[편집]

[각주]

2.21. "L" 확장[편집]

[각주]

2.22. "T" 확장[편집]

[각주]

2.23. "N" 확장[편집]

[각주]

2.24. "H" 확장[편집]

[각주]

2.25. "S" 확장[편집]

[각주]

2.26. "J" 확장[편집]

[각주]
파일:CC-white.svg 이 문서의 내용 중 전체 또는 일부는 2023-11-02 13:00:29에 나무위키 RISC-V/명령어 목록 문서에서 가져왔습니다.


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